HDLbits Solutions

HDL Bits Solutions Repository

Welcome to the HDL Bits Solutions repository! Stucked while solving HDL Bits problems. This space is dedicated to sharing solutions for the exercises on the HDL Bits website.

Table of Contents ?

• Repository Structure
• About HDL Bits
• Usage
• Contact

Repository Structure

The repository is organized to make it easy to navigate and find the solutions you need:

Important

1. Getting Started ??

• 1.1. Step One
• 1.2. Zero

2. Verilog Language ??

• 2.1. Basic ?

  • 2.1.1. Simple wire
  • 2.1.2. Four wires
  • 2.1.3. Inverter
  • 2.1.4. And Gate
  • 2.1.5. Nor Gate
  • 2.1.6. Xnor Gate
  • 2.1.7. Declaring Wire
  • 2.1.8. 7458 Chip
• 2.2. Vectors ?

  • 2.2.1. Vector
  • 2.2.2. Vector1
  • 2.2.3. Vector 2
  • 2.2.4. Vector gates
  • 2.2.5. Gate 4
  • 2.2.6. Vector 3
  • 2.2.7. Vector Reverse
  • 2.2.8. Vector 4
  • 2.2.9. Vector 5
• 2.3. Modules Hierarchy ?

  • 2.3.1. Module
  • 2.3.2. Module-Position
  • 2.3.3. Module-Name
  • 2.3.4. Module-Shift
  • 2.3.5. Module-Shift8
  • 2.3.6. Adder 1
  • 2.3.7. Adder 2
  • 2.3.8. Carry Select Adder
  • 2.3.9. Adder cum Subtractor
• 2.4. Procedures ?

  • 2.4.1. Always Block - Combinational
  • 2.4.2. Always Block - Clocked
  • 2.4.3. If Statement
  • 2.4.4. If latch
  • 2.4.5. Case Statement
  • 2.4.6. Priority Encoder
  • 2.4.7. Encoder with casez
  • 2.4.8. Avoiding Latch
• 2.5. More Verilog Feature ?

  • 2.5.1. Conditional Ternry Operators
  • 2.5.2. Reduction Operators
  • 2.5.3. Reduction- Even wider gates
  • 2.5.4. For loop vector reversal
  • 2.5.5. For loop population count
  • 2.5.6. Generate- for loop adder
  • 2.5.7. Generate- for loop BCD Adder

3. Circuits ??

• 3.1. Combinational Logic ?

  • 3.1.1 Basic Gates ?

    • 3.1.1.1. Wire
    • 3.1.1.2. Ground
    • 3.1.1.3. NOR Gate
    • 3.1.1.4. Another Gate
    • 3.1.1.5. Two Gates
    • 3.1.1.6. More Logic Gate
    • 3.1.1.7. 7420 Chip
    • 3.1.1.8. Truth Table
    • 3.1.1.9. Two Bit Equality
    • 3.1.1.10. Sample Circuit A
    • 3.1.1.11. Sample Circuit B
    • 3.1.1.12. Combine A and B
    • 3.1.1.13. Ring or Vibrate?
    • 3.1.1.14. Thermostat
    • 3.1.1.15. Population Counter
    • 3.1.1.16. Gate and Vector
    • 3.1.1.17. Even Longer Vector
  • 3.1.2 Multiplexer ?

    • 3.1.2.1. 2 to 1 Multiplexer
    • 3.1.2.2. 2 to 1 Bus Multiplexer
    • 3.1.2.3. 9 to 1 Multiplexer
    • 3.1.2.4. 256 to 1 MUX
    • 3.1.2.5. 256 to 1 4-bit MUX
  • 3.1.3 Arithematic Circuits ?

    • 3.1.3.1. Half Adder
    • 3.1.3.2. Full Adder
    • 3.1.3.3. 3-bit Binary Adder
    • 3.1.3.4. Adder
    • 3.1.3.5. Signed Addition Overflow
    • 3.1.3.6. 100-bit Binary Adder
    • 3.1.3.7. 4-bit BCD Adder
  • 3.1.4 K-Maps to Circuit ?

    • 3.1.4.1. 3 Variable
    • 3.1.4.2. 4 Variable 1
    • 3.1.4.3. 4 Variable 2
    • 3.1.4.4. 4 Variavle 3
    • 3.1.4.5. Minimum SOP and POS
    • 3.1.4.6. K-Map 1
    • 3.1.4.7. K-Map 2
    • 3.1.4.8. K-Map implemented with MUX
• 3.2. Sequential Logic ?

  • 3.2.1 Latches and Flip-Flops ?

    • 3.2.1.1. D flip-flop
    • 3.2.1.2. D flip-flops
    • 3.2.1.3. DFF with Reset
    • 3.2.1.4. DFF with Reset Value
    • 3.2.1.5. DFF with Asynchronous Reset
    • 3.2.1.6. DFF with Enable
    • 3.2.1.7. D Latch
    • 3.2.1.8. DFF 1
    • 3.2.1.9. DFF 2
    • 3.2.1.10. DFF + Gate
    • 3.2.1.11. MUX + DFF 1
    • 3.2.1.12. MUX + DFF 2
    • 3.2.1.13. DFF and Gates
    • 3.2.1.14. Circuit from Truth Table
    • 3.2.1.15. Detect an Edge
    • 3.2.1.16. Detect Both Edge
    • 3.2.1.17. Edge Capture Register
    • 3.2.1.18. Dual-edge Triggered Flip-flop
  • 3.2.2 Counters ?

    • 3.2.2.1. Four-bit Counter
    • 3.2.2.2. Decade Counter
    • 3.2.2.3. Decade Counter Again
    • 3.2.2.4. Slow Decade Counter
    • 3.2.2.5. Counter 1-12
    • 3.2.2.6. counter 1000
    • 3.2.2.7. 4 digit Decimal Counter
    • 3.2.2.8. 12-hour Clock
  • 3.2.3 Shift Registers ?

    • 3.2.3.1 4-bit Shift Register
    • 3.2.3.2 Left-Right Rotator
    • 3.2.3.3 Left-Right Arithematic Shift by 1 or 8
    • 3.2.3.4 5-bit LFSR
    • 3.2.3.5 3-bit LFSR
    • 3.2.3.6 32-bit LFSR
    • 3.2.3.7 Shift Register 1
    • 3.2.3.8 Shift register 2
    • 3.2.3.9 3 input LUT
  • 3.2.4 More Circuits ?

    • 3.2.4.1. Rule 90
    • 3.2.4.2. Rule 110
    • 3.2.4.3. Conways Game of Life 16X6
  • 3.2.5 Finite State Machines ?

    • 3.2.5.1. Simple FSM 1 (async reset)
    • 3.2.5.2. Simple FSM 1 (sync reset)
    • 3.2.5.3. Simple FSM 2 (async reset)
    • 3.2.5.4. Simple FSM 2 (sync reset)
    • 3.2.5.5. Simple State Transition 3
    • 3.2.5.6. One Hot FSM
    • 3.2.5.7. Simple FSM 3 (async reset)
    • 3.2.5.8. Simple FSM 3 (sync reset)
    • 3.2.5.9. Design a Moore FSM
    • 3.2.5.10. Lemming 1
    • 3.2.5.11. Lemming 2
    • 3.2.5.12. Lemming 3
    • 3.2.5.13. Lemming 4
    • 3.2.5.14. One Hot FSM
    • 3.2.5.15. PS2 Packet Parser
    • 3.2.5.16. PS2 Packet Parser and Datapath
    • 3.2.5.17
    • 3.2.5.18
    • 3.2.5.19
    • 3.2.5.20
    • 3.2.5.21
    • 3.2.5.22
    • 3.2.5.23
    • 3.2.5.24
• 3.3. Building Larger Circuit ?

  • 3.3.1.

4

• 4.1

  • 4.1.1
• 4.2

  • 4.2.1

About HDL Bits ?

HDL Bits is a website containing a collection of small circuit design exercises for practicing digital hardware design using Verilog Hardware Description Language (HDL). The exercises range from tutorial-style problems for beginners to increasingly challenging tasks that test and improve your circuit design skills. Each problem requires you to design a small circuit in Verilog. HDLBits gives you immediate feedback on the circuit module you submit. Your circuit is checked for correctness by simulating with a set of test vectors and comparing it to our reference solution.

How to use HDLBits ▶️

1. Use any browser and go to HDLBits site.
2. Choose a problem: Browse the problem set or go to the first problem.
3. Write a solution in Verilog.
4. Submit, simulate, and debug if necessary

If you want to track your progress or move to another browser, create a username and password so you can log in from elsewhere.

Usage

How to Find Solutions ?

Navigate to problems from Repository Structure and select needed directory to find solutions to specific HDL Bits exercises. Each challenge directory may contains:

• problem_statement.md: The original problem statement.
• solution_verilog.v: Solution written in Verilog.
• output_wavwform.png: Simulated result's waveform.
• testbench.sv: Testbench to verify the solution.

Contact ?

Have questions, suggestions, feedback, or you find something wrong here? We'd love to hear from you! Reach out at ....

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