CraneCPU

CraneCPU

Hardware experiment of computer system integration courses at Zhejiang University

Warning : For reference only, please do not copy

Experimental progress

The system integration course will gradually implement a RISC-V five-level pipeline CPU, and implement exception handling, branch prediction, cache, MMU and other functions, and run a simple kernel written by yourself on it.

This repo records the experimental progress through branches, tags, etc. and preserves the results of each stage.

• System I lab5-1/lab5-2: Single-cycle CPU
• extra: Single-cycle CPU with privileged instructions/exception handling
• System II lab1: Pipeline CPU (stall)
• System II lab2: Pipeline CPU (forwarding)
• System II lab7: Pipeline CPU with privileged instructions/exception handling
  • Note : In fact, this lab is not perfect, only the csrr and csrw can run, the privilege level basic functions are not complete, and need to be improved
• System III lab1: Pipeline CPU with Dynamic Branch Prediction
  • If you use the provided experimental framework instead of your own, you will not put it in the repo
• System III lab2: Pipeline CPU with Cache
  • If you use the provided experimental framework instead of your own, you will not put it in the repo
• System III lab Xpart: Software and hardware integration experiment, the main part is to implement MMU and debug kernel
  • RV64IZicsr All instructions (excluding fence ebreak wfi)
  • Includes two privilege levels: Supervisor and User
  • Implements two pagination modes, including Bare and Sv39
  • Support serial port output
  • Show slides in: slides.tonycrane.cc/sys3-xpart-pre

Experimental environment

In class, we used vivado and the Nexys A7-100T FPGA development board for experiments.

For the convenience of development/simulation on non-Windows platforms, Icarus Verilog and GTKWave are used for simulation.

Compilation and simulation

A Makefile is used to integrate compilation, simulation and other operations:

• make : compile, simulate, and open GTKWave to view the waveform
• make compile : Compile
• make simulate : Simulate and open GTKWave to view the waveform

The path of GTKWAVE needs to be specified through GTKWAVE=/path/to/your/gtkwave .

statement

I haven't learned verilog seriously, and I've written it very much. Anyway, I can just run, and I'm too lazy to change it when I run. For reference only, the reference value may not be that great (x, then it is for recording only (✓

LICENSE

All of them are written entirely based on the starter code, so just use a MIT license.