3ph_pll

Three phase (3-PH) DSOGI Phase Lock Loop (PLL)

Dependencies

Roadmap

• Angle Lock
• Phase Swap Detection
• Realtime Phase Fault Detection
• Generated Code
• Code Tested on STM32F7 (code on stm32.zip)
• Not using Volder's algorithm instead using approximations requiering a sampling of 10kHz

Demo

Worse case, when the phase of the Voltage phase is pi radians of offset at the start, thus having the maximum error.

65Hz input

55Hz input

45Hz input

Authors

• Angel Rodriguez [[email protected]]

Acknowledgements

• [1] Pinto J, Carvalho A, Rocha A, Araújo A. Comparison of DSOGI-Based PLL for Phase Estimation in Three-Phase Weak Grids. Electricity. 2021; 2(3):244-270.